AIM:
Generate
square wave at P0.4 with PLL (Fosc=12 MHz and Cclk = 48 MHz).
THEORY:
PLL
is a block that allows multiplying the input frequency. The multiplication
factor can be an integer or a rational number. There are two PLL modules in the
LPC2141/2/4/6/8 microcontroller. The PLL0 is used to generate the CCLK clock
(system clock) while the PLL1 has to supply the clock for the USB at the fixed
rate of 48 MHz Structurally these two PLLs are identical with exception of the
PLL interrupt capabilities reserved only for the PLL0. The PLL0 and PLL1 accept
an input clock frequency in the range of 10 MHz to 25 MHz only.