Thursday, 27 June 2013

Study of PLL (Phase Locked Loop) Generate square wave at P0.4 with PLL (Fosc=12 MHz and Cclk = 48 MHz) using ARM LPC2148....


AIM: Generate square wave at P0.4 with PLL (Fosc=12 MHz and Cclk = 48 MHz).

THEORY:
PLL is a block that allows multiplying the input frequency. The multiplication factor can be an integer or a rational number. There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is used to generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the USB at the fixed rate of 48 MHz Structurally these two PLLs are identical with exception of the PLL interrupt capabilities reserved only for the PLL0. The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz only.
The input frequency is multiplied up the range of 10 MHz to 60 MHz for the CCLK and 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is shown in fig.
                PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values are controlled by the PLLCFG register. These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip operations, including the Watchdog Timer, are dependent on the PLL0 when it is providing the chip clock, accidental changes to the PLL setup could result in unexpected behavior of the microcontroller. The same concern is present with the PLL1 and the USB. The protection is accomplished by a feed sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register. The PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.
The PLL output frequency (when the PLL is both active and connected) is given by:
                   
                    CCLK = M × FOSC or CCLK = FCCO / (2 × P)

The CCO frequency can be computed as:

            
                    FCCO = CCLK × 2 × P or FCCO = FOSC × M × 2 × P

The PLL is controlled by the registers shown in Table 1 More detailed descriptions follow.
Table 1: Special function registers (SFR) concerned with PLL.
Registers
Function
PLLCON

PLL Control Register. Holding register for updating PLL control bits. Values written to this register do not take effect until a valid PLL feed sequence has taken place.
PLLCFG
.
PLL Configuration Register. Holding register for updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence has taken place
PLLSTAT

PLL Status Register. Read-back register for PLL control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they will not reflect the current PLL state. Reading this register provides the actual values controlling the PLL, as well as the status of the PLL.
PLLFEED

PLL Feed Register. This register enables loading of the PLL control and configuration information from the PLLCON and PLLCFG registers into the shadow registers that actually affect PLL operation.

Table 2: PLL Control register
Bit
Symbol
Description
0
PLLE
1= PLL Enable, 0 = PLL Disable
1
PLLC
PLL connect when PLLE and PLLC are 1 then PLL is connect to the external System.
Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values.  Connecting the PLL causes the processor and all chip functions to run from the PLL output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given
Table 3: PLL Configuration register
Bit
Symbol
Description
4:0
MSEL
PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations.
6:5
PSEL
PLL Divider value. Supplies the value "P" in the PLL frequency calculations.
The PLLCFG register contains the PLL multiplier and divider values. Change to the PLLCFG register do not take effect until a correct PLL feed sequence has been given.

Table 4: PLL Status register
Bit
Symbol
Description
4:0

MSEL
Read-back for the PLL Multiplier value. This is the value currently used by the PLL
6:5

PSEL
Read-back for the PLL Divider value. This is the value currently used by the PLL
7 

-
Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
8

PLLE
Read-back for the PLL Enable bit. When one, the PLL is currently activated. When zero, the PLL is turned off. This bit is automatically cleared when Power-down mode is activated.
9
PLLC
Read-back for the PLL Connect bit. When PLLC and PLLE are both one, the PLL is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.
10

PLOCK
Reflects the PLL Lock status. When zero, the PLL is not locked. When one, the PLL is locked onto the requested frequency.


Table 5: VPB Divider register
Bit
Symbol
Value
Description
1:0
VPBDIV
00
VPB bus clock is one fourth of the processor clock

01
VPB bus clock is the same as the processor clock.

10
VPB bus clock is one half of the processor clock.

11
Reserved. If this value is written to the VPBDIV register, it has no effect (the previous setting is retained).
Table 6: PLL Feed register
Bit
Symbol
Description
7:0
PLLFEED
The PLL feed sequence must be written to this register in order for PLL configuration and control register changes to take effect.
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
PORCEDURE:
If a particular application uses the PLL0, its configuration may be determined as follow:
   1.Choose the desired processor operating frequency (CCLK). This may be based on processor throughput requirements, need to support a specific set of UART baud rates, etc. Bear in mind that peripheral devices may be running from a lower clock than the processor.
    2.Choose an oscillator frequency (FOSC). CCLK must be the whole (non-fractional) multiple of FOSC.
     3. Calculate the value of M to configure the MSEL bits. M = CCLK / FOSC. M must be in the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M 1 (see Table 7.
      4.  Find a value for P to configure the PSEL bits, such that FCCO is within its defined frequency limits. FCCO is calculated using the equation given above. P must have one of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 8).



Table 7: PLL Multiplier values                                           
MSEL Bits
 (PLLCFG bits [4:0])
Value of M
 00000
1
00001
2
00010
3
00011
4
....
….
11110
31
11111
32
Table 8: PLL Divider values
PSEL Bits (PLLCFG bits [6:5])
Value of P
00
1
01
2
10
4
11
8

OBSERVATIONS:
1.   Observe pins P0.4 without PLL and Checkout frequency at P0.4.
2.   Observe pins P0.4 with PLL and Checkout frequency at P0.4.
3.   Observe output in proteus with Oscilloscope.

Generate square wave at P0.4 with PLL (Fosc = 12 MHz and Cclk = 48 MHz).
In Embedded c:
 #include <LPC214X.H>
void init_PLL(void);
void delay(void);
int main(void)
{  
 PINSEL0 = 0x00;
 IODIR0 = 0x000000F0;
 init_PLL();                
 while(1)
    {      
        IOCLR0 = 0x00000010; 
        delay();             
        IOSET0 = 0x00000010;
        delay();             
    }  
}
void init_PLL(void)
{         
PLL0CFG = 0x00000023;                                         
 PLL0CON = 0x00000001;           // Enable the PLL   
 PLL0FEED = 0x000000AA;          // Update PLL registers with feed sequence
 PLL0FEED = 0x00000055;
while (!(PLL0STAT & 0x00000400)) // test Lock bit
    { ; }

    PLL0CON = 0x00000003;           // Connect the PLL 
    PLL0FEED = 0x000000AA;          //Update PLL registers
    PLL0FEED = 0x00000055;  
    VPBDIV = 0x00000002;            //Set the VLSI peripheral bus
}
void delay(void)
{
    unsigned int i;
    for(i=10000; i>0; i--)
    {;}
  }


  
Square wave output:
With PLL 48 MHz

48*10^6 Cycles passes in 1 sec


Without PLL
12 MHz

  
12*10^6 Cycles passes in 1 sec


 Proteus design:

48 MHz:

 12 MHz:



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